Serial configuration memories are devices used to initialize programmable logic devices, such as field programmable gate arrays (FPGAs). When a device such as an FPGA powers up, each of its logic blocks must be configured for a specific logic operation and its programmable interconnects must be configured to provide routing among the logic blocks to implement the intended logic function. The configuration information takes the form of a bitstream which feeds into the FPGA and is stored in the device, where the bits define logic and routing of the FPGA elements.
A serial configuration memory is the device which contains the configuration bitstream. A serial configuration memory consists of a memory array such as a PROM (programmable read only memory) or EEPROM (electrically erasable programmable read only memory), an address counter, and supporting logic to provide programming and reset control. The address counter is tied to a clock input line and is incremented on each rising or falling edge of a clock signal. The counter output serves to address each bit of the memory array, producing a bitstream which is serially output to an FPGA.
Many of today's personal electronic devices are powered by an independent source, namely a battery, and so there is always a concern for conserving power wherever possible. The desire to minimize power consumption pervades every aspect of the design of these devices. FPGAs find use in many such devices, including laptop computers, notepad computers, and cellular telephones. Configuration memories, therefore, present an opportunity where improvements can be made to minimize power consumption.
An aspect of modern FPGAs is their ability to be reconfigured in-system. Thus, the functionality of an FPGA can be dynamically altered while the system is running. This capability provides a high degree of flexibility for the system to adapt its operation in response to external conditions. For example, in an FPGA configured as a digital filter, its filter parameters can be altered simply by loading in a different set of filter coefficients when the need to do so is detected. However, reconfiguring an FPGA in real time requires the ability to download a new configuration bitstream without imposing a delay that would detrimentally impact system functionality. Thus, high speed operation is another area for improvement in configuration memory devices.
Prior art configuration memories output their entire contents in the form of a bitstream beginning with the first location of memory. In-system reconfiguration of an FPGA, however, requires access to any one of a number of configuration bitstreams that might be contained in a configuration memory, each bitstream having its own beginning address within the memory. It is a desire, therefore, to provide a configuration memory wherein an arbitrary beginning address can be specified. More generally, it is desirous to have the capability of arbitrarily addressing the memory device.